1. Field of the Invention
The present invention relates to a method for inspecting an insulator with a library of optic images and, more particularly, to a method for monitoring a uniformity of STI Shallow Trench Isolation) in CMP (Chemical Mechanical Polishing) process in the fabrication process of semiconductor device.
2. Background of the Related Art
When a fault occurs for the pattern of a middle process during fabrication process of semiconductor device, yield of the device decreases. Therefore, methods of inspecting the pattern in the middle process of the fabrication process are being vigorously studied. Such methods include systems and methods based on the identification of a visible pattern fault in the optic image of a wafer, that is, the comparison of features between a basic image and a test image. The features include size, shape, average pixel strength, a center of gravity, diameter, region, and a variance.
For example, a conventional method is based on a voltage-contrast image of a wafer with a scanning electronic beam. The method which inspects faults from the voltage-contrast image is based on the difference of pixel-strength values between an image of a pattern to inspect and the basic image. To extract the faults, these two images or image regions are corrected for the differences in the brightness and the contrast and then arranged. Next, the difference image is made by obtaining the difference of the pixel-strength value for each pixel. By determining a boundary value in the difference image, a fault image is made such that the pixel value becomes binary. The characteristics in the fault image that satisfy particular states such as minimum size, shape, and strength are regarded as faults. Then, statistics of the faults in the images are calculated and reported. For instance, the most serious fault and the number of faults are repeated for each image. As the most serious fault is first handled and analyzed in reviewing the images based on these statistics, reviewing time is considerably diminished. An advantage of this method lies in that it does not require the electrical features or the knowledge of the structure in the voltage-contrast images, and just the alignment and the image normalization can correct the total difference within the images or the image regions. Thus, without the electrical pattern being inspected in advance, the voltage-contrast fault can be detected in this method.
However, the weak point of the above method is that any image difference is regarded as a potential fault. So, it is difficult to tell the difference between an obvious fault and an unnecessary fault which is actually not a fault, but an insignificant error on the surface or artificial objects for images. Several artificial objects in the inspection procedure cause an image alignment error, a local image distortion, and nonlinearity in scanning process for obtaining a voltage-contrast image. The obvious faults occur so rare in general that the number of the unnecessary faults can be much more than that of the obvious faults. More than 90% of reported faults can be classified into the unnecessary faults in conventional pixel-substrate inspection system. To separate the unnecessary faults from the obvious faults require much time and endeavor by a man. The high proportion of the unnecessary faults and the requirement of inspection by a man make it difficult to improve the performance of an inspection processor, the usage of which becomes more frequent in the fabrication of a semiconductor wafer. To decrease the proportion of the unnecessary faults due to the alignment error, the conventional solutions such as a precise wafer-stage positioning, uniform and reproducible imaging, and an improved fault-detection algorithm require many processes, mcuh time, and many hardware devices.
On the other hand, a method for maintaining a planarization of insulating layer, which measures only thickness of monitoring pattern, also has a limitation to gather data all over the inspection range and a restriction on the size and the location of the monitoring pattern. So it may not represent the degree of uniformity of the fine circuit inside a chip. Moreover, as the line width of a circuit gets gradually thinner, the feature of the monitoring pattern as a chip representative gets more dilute. Thus, the maintenance of the planarization of the insulating layer only by the conventional thickness measurement is practically faced with the limit.
U.S. Pat. No. 5,964,643 discloses apparatus and method for in-situ monitoring of chemical mechanical polishing operations. An in-situ method of measuring uniformity of a layer on a substrate during polishing of said layer, where the method includes the steps of directing a light beam toward the layer during polishing; monitoring an interference signal produced by the light beam reflecting off of the substrate; and computing a measure of uniformity from the interference signal.
U.S. Pat. No. 5,365,340 discloses apparatus and method for measuring the thickness of thin films. A measurement instrument which detects the thickness of the outer layer of a wafer, includes a filtered white light source forming an aperture image. The white light source includes a halogen lamp, a condensing lens, a circular aperture, a collimator lens, a narrow band filter wheel, and a second collimator lens. A monochromatic beam generated by this filtered white light source illuminates the entire surface of the wafer with collimated light that has passed through a third collimator lens. The light reflected off the wafer returns through the third collimator lens and forms an aperture image upon an optical device which redirects this image to a charge coupled device (CCD) camera. The image is converted to a map of measured reflectance data by a digitizing circuit and a computer. This map of measured reflectance data is then self-normalized and compared to reference reflectance data to generate a map of the outer layer thickness profile of the wafer.
U.S. Published Patent No. 2002-0072133 discloses a method and apparatus for numerically analyzing a growth degree of grains grown on a surface of a semiconductor wafer. A method and apparatus for numerically analyzing a growth degree of grains grown on a surface of a semiconductor wafer, in which the growth degree of grains is automatically calculated and numerated through a computer by using an image file of the surface of the semiconductor wafer scanned by an SEM. A predetermined portion of a surface of the wafer is scanned using the SEM, and the scanned SEM image is simultaneously stored into a database. An automatic numerical program applies meshes to an analysis screen frame and selects an analysis area on a measured image. Thereafter, a smoothing process for reducing an influence of noise is performed on respective pixels designated by the meshes using an average value of image data of adjacent pixels. A standardization process is then performed, based on respective images in order to remove a brightness difference between the measured images. After comparing standardized image data values of the respective pixels with a predetermined threshold value, the number of pixels whose standardized image data value is greater than the threshold value is counted. The growth degree of grains on the surface of the wafer is calculated by numerating a ratio of the counted number with respect to a total number of the pixels contained within the analysis target image.